This volume presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behaviour) levels of the design hierarchy, which are often the levels that yield the most power savings. It describes power estimation and optimization techniques for use during high-level (behavioural synthesis), as well as for designs expressed at the register-transfer or architecture level. The book surveys research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. It should be of use to students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.