Digital Signal Processing (DSP) architectures utilizing full precision multipliers require an ever increasing bit width with large power consumption. Truncated multipliers trade power consumption in the multiplication process with degradation in overall accuracy. Moreover, another optimization approach based on Booth multiplication algorithm is also analyzed. Radix-22 Booth encoded Two's Complement System multiplier decreases the partial product terms by factor of 2 whereas in radix-23 Booth encoded TCS multiplier, the number of partial products is reduced to one-third. However higher order radix-23 Booth multiplier suffers from hard multiple (3X) problem where X denotes the multiplicand whenever 3X is generated by Carry Propagation Adder. Due to this problem area and delay reduction in case of radix-23 multiplier is much less than the theoretical results. To avoid this problem Parallel-Prefix Adder is used to calculate the 3X. Proper delay and area analysis of radix-22, radix-23 and radix-23 with PPA is done. Further improvement in terms of speed of multiplier is obtained by employing a method known as Booth encoded multi-modulus multiplier.