These proceedings contain the papers presented at theAdvanced Research Working Conference on Correct HardwareDesign Methodologies, held in Arles, France, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIP Working Group 10. 2. Formal verification is emerging as a plausible alternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation of functional and timingbehavior is a major bottleneck in current VLSI designsystems, slowing the arrival of products in the marketplacewith its associated increase in cost. From being apredominantly academic area of study until a few years ago,formal design and verification techniques are now beginningto migrate into industrial use. As we are now witnessing anincrease in activity in this area in both academia andindustry, the aim of this working conference was to bringtogether researchers and users from both communities.