The revolution in wireless communications sets new requirements for transceivers (transmitter-receivers). Higher operating frequencies, lower power consumption and very high degree of integration, are specifications which require design approaches quite different from classical RF design techniques. The integratability and power consumption reduction of the digital component should further improve with the continued downscaling of technologies. This is, however, completely different for the analog transceiver front-end, the component which interfaces between the antenna and the digital signal processor. The analog front-end's integratability and power consumption are closely related to the physical limitations of the transceiver topology and not so much to the scaling of the used technology. Providing a comprehensive treatment of the design of transceivers for use in wireless communication systems, the book overviews existing transceiver design and goes on to introduce new multi-path receiver and transmitter topologies.
It also presents a formal methodology for the high-level design of transceiver architectures and fully illustrates its use in the design of a low-IF/direct upconversion GSM transceiver front-end. This text further demonstrates its practical nature by containing concluding chapters which study both the integration of RF building blocks in CMOS and the capabilities of deep submicron CMOS used in combination with the new transceiver topologies for the implementation of wireless transceiver front-ends in the 1 to 2 GHz range.