This monograph addresses the problem of device layout for high-performance custom analog cells. In particular, an alternative placement and routing formulation is proposed that is designed to minimize the cost in layout quality that is traditionally associated with analog layout automation. The goal of analog layout is to minimize the effects of layout induced performance degradation while, at the same time, maximizing the area utilization of the circuit. Human layout experts observe a variety of analog-specific layout constraints and exploit a range of geometric optimizations to achieve these performance and density goals. This work is directed at discovering how these constraints and optimizations can best be incorporated into automatic layout optimization. Two of the products of this research are a analog device-level placer, KOAN, and a analogue device-level router, ANAGRAM II [40], which incorporate a more comprehensive set of layout constraints and geometric optimizations than in any previous systems. The work focuses on the formulation, algorithms, and certain relevant implementation details of KOAN and ANAGRAM II.